This invention relates to semiconductor memory devices and more particularly to a dynamic memory device which functions as a static memory device.
The most widely used semiconductor memory devices at present are one-transistor dynamic memory cells as described in U.S. Pat. No. 3,940,747, issued Feb. 24, 1976, to Kuo and Kitagawa, assigned to Texas Instruments. Higher density versions of these dynamic memory systems are shown in Electronics magazine, Sept. 13, 1973, pp. 116-121, Feb. 19, 1976, at pp. 116-121, May 13, 1976, pp. 81-86, and Sept. 28, 1978, pp. 109-116. These high density devices use one-transistor dynamic memory cells which have the advantage of very small size, and thus low cost, but have the disadvantage of requiring external refresh systems. Each row of an array of cells must be addressed above every two milliseconds to restore the data because the stored voltages will leak off the capacitors in the memory cells. Refresh imposes both programming and hardware burdens on the system.
Usually refresh is accomplished by sequentially accessing a bit in a row of a dynamic RAM in either a burst refresh mode where consecutive access cycles are used to refresh all rows, or in a distributed refresh mode where the refresh cycles are distributed over the entire refresh period. In either case, the memory system requires a counter (eight bits long for 256 rows, for example) for the refresh address, plus a system interrupt mechanism to allow the refresh to occur, and a timer to indicate when refresh should occur, whether burst or distributed mode is used. In a large memory system the overhead circuitry to provide the refresh control is a small part of the system cost, so dynamic RAMs are widely used in medium to large memory systems. However, in small memory systems of the type usually associated with small minicomputers and microprocessors the refresh control circuitry is a significant portion of the system cost, so static RAMs are often substituted for dynamic RAMs in spite of the higher cost of static RAMs. A single-board microcomputer, for example, may need to use one-third of the board space for refresh control if dynamic RAMs are used.
The typical static RAM cell requires six transistors, or four transistors and two polysilicon resistors, so the cell size is much greater than the one transistor and one capacitor used in dynamic RAMs. Static cells which provide reduced area are shown in U.S. Pat. No. 4,110,776 issued to Rao, Stanczak, Lien and Bhatia, assigned to Texas Instruments. Various types of "self-refreshing" cells have been demonstrated, such as in U.S. Pat. Nos. 3,955,181 issued to Joseph H. Raymond, Jr., 4,092,735, 4,139,785 or 4,142,111 issued to David J. McElroy, and 4,070,653 issued to Rao, Rogers and McElroy, all assigned to Texas Instruments; these self-refresh cells provide apparently static operation in that refresh is accomplished without addressing the cells. Still, the cell size and cost per bit for static RAMs or pseudo static RAMs have not reached that of dynamic RAMs.
In copending application Ser. No. 918,891, now U.S. Pat. No. 4,207,618, filed June 26, 1978, by White and Rao and assigned To Texas Instruments, a pseudo static memory is disclosed which is a standard dynamic RAM having an on-chip row address counter to produce refresh addresses. The counter is incremented by refresh commands from external to the chip. A similar system is shown at pp. 94-97 of Electronics Design, Sept. 1, 1979.
It is a principal object of this invention to provide improved memory systems and devices made in semiconductor integrated circuits. Another object is to provide an improved "pseudo static" type MOS memory device, particularly a memory device of small size (using one transistor dynamic cells, for example) and not requiring refresh address or command inputs. An additional object is to provide small area pseudo static memory elements in semiconductor integrated circuits, particularly memory devices employing dynamic cell arrays with all of the refresh overhead incorporated on the same chip. A further object is to provide a pseudo static RAM wherein refresh is invisible to the CPU.